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Philips Semiconductors
PCF85102C-2
256 × 8-bit CMOS EEPROM with I 2 C-bus interface
6. Pinning information
6.1 Pinning
A0
1
8 V DD
Fig 2. Pin con?guration.
6.2 Pin description
Table 4:
Pin description
A1 2
A2 3
VSS 4
002aaa248
7
6
5
N.C.
SCL
SDA
Symbol
A0
A1
A2
V SS
SDA
SCL
N.C.
V DD
7. Device addressing
Pin
1
2
3
4
5
6
7
8
Description
address input 0
address input 1
address input 2
negative supply voltage
serial data input/output (I 2 C-bus)
serial clock input (I 2 C-bus)
no connect
positive supply voltage
Table 5:
Device address code
Selection
Device code
Chip Enable
R/W
Bit
Device
b7 [1]
1
b6
0
b5
1
b4
0
b3
A2
b2
A1
b1
A0
b0
R/W
[1]
The Most Signi?cant Bit (MSB) ‘b7’ is sent ?rst.
A2, A1, A0 are hardware selectable pins.
A system could have up to eight PCF85102C-2 devices on the same I 2 C-bus,
equivalent to a 16 kbit EEPROM or 8 pages of 256 bytes of memory.
The eight addresses are de?ned by the state of the A0, A1, A2 inputs (logic level ‘1’
when connected to V DD , logic level ‘0’ when connected to GND). Figure 3 shows the
various address combinations.
9397 750 14216
? Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 04 — 22 October 2004
4 of 20
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